This disclosure relates to a buffer control signal generation circuit.
As the development of the technology for computer systems or electronic communications steadily has evolved, semiconductor devices used for storing information have become cheaper, physically smaller, and larger with respects to data capacity. As a result, increasing demands for efficient energy consumption are being imposed on these types of semiconductor memory devices in order to cut down unnecessary current dissipation.
A general cell array layout for storing data in dynamic random access memory (DRAM) semiconductor devices is usually configured to include a plurality of memory cells coupled to word and bit lines which usually forms a web or matrix like structure. Each memory cell is usually composed of one transistor and one capacitor.
In these types of DRAM devices, when a reading operation begins, data which is stored in a memory cell is loaded into a pair of bit lines and detected/amplified by using a sense amplifier. The amplified data is then output through a data output buffer by way of local and global input/output lines. On the other hand, when a writing operation begins in these DRAM devices, data input through the data input/output buffer is loaded into a pair of bit lines through local and global input/output lines and then stored in a memory cell.
As shown in FIG. 1, a general operation of controlling the data input/output buffer used in the writing operation of the DRAM device is as follows.
First, when an external write command ECAin at a time t1 is received, then a buffer enable signal DBUF_EN is generated at a high level state at a time t2. The buffer enable signal DBUF_EN of high level state enables a buffer control signal ENDINDSB to be activated in a low level state to drive a data input buffer (not shown).
Next, if a burst operation is terminated at a time t5 and a burst period signal FYBSTN is inactivated to a low level state, a burst end signal BENDB is activated in a low level state at a time t6. As a result the buffer control signal ENDINDSB is inactivated in a high level state to stop driving the data input buffer.
Meanwhile, data DIN input through the data input buffer are all received until the time t5 in sync with strobe signals DS and DSB applied thereto in compliance with predetermined write latency.
As such, the data DIN are all input until the time t5, and the data input buffer uselessly continues to operate even until time t6.